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By John Bainbridge

Asynchronous System-on-Chip Interconnect describes using a completely asynchronous system-bus for the modular building of built-in circuits. is simply awakening to some great benefits of asynchronous layout in keeping off the issues of clock-skew and a number of clock-domains, an din parallel with this can be coming to grips with highbrow estate (IP) established layout flows which emphasise the necessity for a versatile interconnect technique. during this ebook, John Bainbridge investigates the layout of an asynchronous on-chip interconnect, taking a look at the entire phases of the layout from the alternative of wiring structure, via asynchronous signalling protocols to the better point difficulties excited by helping cut up transactions. The MARBLE bus (the first asynchronous SoC bus) utilized in a advertisement demonstrator chip containing a mix of asynchronous and synchronous macrocells is used as a concrete instance during the book.

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92_2 _________ _ : - . r- - . , - -1- t r- 1- I· I... J -----~ ~~-- SO . ON TIH( ILINJ ISO . 3-----AL2 = (}--- -- -- --· ....... ·r· 1 i t" Uj_ 0. J.. t . : - . 1 : ... I/.. " - ---;: 200 . 0N 24 0 . 5 shows the delay from the input of the drive inverter crossing the half-rail voltage to the far end of a single wire on the metal-1 layer (closest to the substrate, hence highest loaded) with no other surrounding wires (hence no crosstalk effects) crossing the half-rail voltage. There are four visible groups of curves which, coming down the page, correspond to drive inverters of strengths 2x, 4x, 8x and 16x the strength of a minimum sized inverter in this techno1ogy.

36 4. 3. A test system with nine wires packed in such an arrangement was simulated. e. the wire at the centre of the 9-wire bundle). The delays were measured between the signals crossing the half-rail voltage. 5 (for the same wire and drivers in isolation) shows that: • the delay of a surrounded wire is about double that for an isolated wire, as expected since the capacitive loading has slightly more than doubled (since most of the capacitive coupling is interlayer, not lateral in this technology); • a significant variation in delay, of up to 2ns is possible as a result of crosstalk.

The physicallayer of this bus hierarchy defines how the wires will be terminated, their separation and their size. These issues are addressed for an asynchronaus SoC bus in this chapter. 1 Wire theory Although a wire in a circuit is often considered to have negligible resistance and capacitance, these assumptions are no Ionger true with submicron silicon feature sizes and all of the parameters of the wire must be considered. Since the circuit elements of a wire are distributed along its length the description of the wire requires a partial differential equation.

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